all: clean vcs_compile sim 

compile:
	iverilog -o ./build/simv \
	./tb_LC3.v \
	./mux16_4to1.v \
	./mux16_8to1.v \
	./mux_2to1.v \
	./half_adder.v \
	./full_adder.v \
	./add_16.v \
	./ALU_3basic_fixed.v \
	./register_16.v \
	./register_mine.v \
	./ram.v \
	./pc.v \
	./pc_reg.v \
	./FSM.v \
	./LC_3.v  \
	./tristate.v \
	./decoder_3to8.v \
	./DFF.v
vcs_compile:
	vcs -sverilog -full64 +v2k -debug_all -f top.f  -top tb_LC_3 -o ./build/simv	

sim:
	./build/simv -l ./build/sim.log

simulate:
	vvp -n ./build/simv #vvp为仿真语句，会生成测试激励中所规定的vcd文件

	
gtkwave:
	gtkwave *.vcd


clean:
	rm -rf cs*
	rm -rf ./build/*
	rm -rf simv* csrc* *.tmp *.vpd *.key *.log
	rm -rf verdi* DVE* *.conf *.rc *.fsdb *.h
